(a) Field of the Invention
The present invention relates to a computer system and, more particularly, to a computer system having a cache memory and a data tracing function.
(b) Description of the Related Art
A computer system generally includes a microprocessor (MPU), a ROM for storing a program for operating the MPU, a RAM for storing read/write data, and a peripheral device. During developing a computer system, a tracing circuit is generally provided to the MPU for examining whether or not the MPU operates expected functions, i.e., for debugging.
Conventionally, the tracing circuit is connected to an external system bus such as an address bus or a data bus to obtain historical data of the MPU 21 at desired timing for storage thereof in the tracing memory. However, if the MPU has a cache memory in the computer system, the tracing circuit connected to the external system bus cannot obtain the data accessed by the MPU when the accessed data is hit in the cache memory.
It is an object of the present invention to provide a computer system having a cache memory for storing instruction code and read/write data, and a tracing circuit capable of tracing read/write data, address thereof and status signals in each instruction without losing real time processing.
The present invention provides a computer system including a pipe-line processor for pipe-line processing of an instruction code in synchrony with a pipe-line clock signal, a system memory for storing data for the pipe-line processor, a system bus for transferring data between the pipe-line processor and the memory, a tracing circuit for storing trace data output from the pipe-line processor, and a trace data transfer circuit for transferring the trace data between the pipe-line processor and the tracing circuit independently of operation of the system bus.
In accordance with the computer system of the present invention, trace data can be supplied to the tracing circuit independently of the system bus without affecting the operation of the system bus and without losing real time processing by the pipe-line processor.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.